FPGA Training Course Day 2

FPGA Training Course Day 2

1) When we declare I/O's with wire, you have to assign them or you shall do it inline as:

wire input1 = SW[6]; //inline assignment
wire input2, input3, input4;
wire [1:0] select = SW[1:0];
wire out;

assign input2 = SW[7];
assign {input4, input3} = SW[9:8];
assign LEDG[0] = out;

2) reg variables can only be assigned in always block, but they can be defined everywhere.

3) input means wire input, output means wire output; you have to write reg to define it reg type.

4) http://opencores.org/ for various designs...
     http://www.fpga4fun.com/ for fun...
    These two sites are very useful for gathering FPGA projects.

5)Simple ALU:
/*This is the start of TOP Module*/
module DE0_TOP
(

input [9:0] SW, // Toggle Switch[9:0]
output [9:0] LEDG, // LED Green[9:0]
);

ALU alu1(SW[3:0],SW[7:4],SW[9:8],LEDG);
endmodule
/*This is the end of TOP Module*/

module ALU(input [3:0] operand1, input [3:0] operand2, input [1:0] oper, output reg [7:0] result);

wire signed [3:0] opr1 = operand1;//You can define as signed!!!
wire signed [3:0] opr2 = operand2;

always @ (*)
begin
case(oper)
 2'b00: result = operand1 + operand2;
 2'b01: result = operand1 - operand2;
 2'b10: result = operand1 * operand2;
 2'b11: result = opr1 * opr2;
default: result = 8'b0;
endcase
end

endmodule

6) With "Inster Template" you can insert template modules, switch cases etc...

7)File -> New-> Verilog HDL File and you can write a module with .v file. Then you can call this module easily.

8) #( parameter SIZE = 32,
   SURE = 32'd50_000_000 )
you can call  binary_counter #(.SURE (12_500_000))b1(.clk(CLOCK_50),....
module with different parameters if you wish by changing SURE value.
Normal call: binary_counter b1(.clk(CLOCK_50)...
Call with input parameter: binary_counter #(.SURE (12_500_000))b1(.clk(CLOCK_50)...

9) You can define parameters as given example (similat to macros in C,C++):

module binary_counter
#(
// Parameter Declarations
parameter SIZE = 32
)

....

10)  Tools->MegaWizard Plug-In Manager contains libraries. You can use these modules if you need. (There are a lot of useful libs.)

11) In order to create a FPGA logic analyzer in the FPGA chip: Tools->Signal Tap II Logic Analyzer
Choose CLOCK_50; Type: Continuous; Pre-Trigger Position to use a trigger and Trigger condition as 1.
Then Double Click on the blank white area to open Node Finder to add the ports and wires or regs that you want to observe. You can use BUTTON[0] as a trigger for instance. Then Run Analysis, the project will be compiled again and after choosing the right device and the compiled file from the right hand side of the screen, click Program Device and Run Analysis again to see what happens. If you set a trigger, it will keep waiting till you trigger it.

12) You can use Qsys under Tools menu to create your own SoC. This is awesome!..You can write your own code and run in your new machine.

13)From File-> Convert Programming File you can convert .sof files to .pof files to write PROM for always use.

We cover a lot of examples even if I cannot share here. This is the end of Day 2!