FPGA Training Course Day1

FPGA Training Course --Day 1--

FPGA is composed of:

• Logic Blocks
• Programmable Interconnect Network
• I/O Blocks
• Clock Management, DLLs&PLLs
• Dedicated Multipliers
• Block RAM (high speed)
• DSP Resources
• Microprocessors (ARM, Atom, PPC)

In fact there are no and/or gates existing in fpga. After we make the FPGA design, a LookUp Table ise constructed and the LUT is used afterwards.

Verilog 4-bit Counter:

module counter(CLOCK, DIRECTION,  COUNT_OUT)

input CLOCK;

input DIRECTION;

.

.

.

VHDL is more functional than Verilog, because it also supports Analog side, not just digital one. Verilog is simpler in syntax.

We will write in Verilog and use Altera Quartus II. 

Altera Board drivers are @ /altera/12.1/quartus/drivers/usb_blaster

You should install drivers first.

Tutorial 1: Simple AND Gate (Schematic Design)

• For our board: Cyclone III EP3C16F484
• Start Altera Quartus  II and create a new project.
• Click new -> Select Block Diagram/Schematic File
• Click Symbol Tool and select /primitives/logic/and2
• Draw your logic design.
• Double click Analysis&Elaboration
• Under Assignments Tab: Select "Pin Planner" to choose your I/O's.
• Open the schematic of board and look for the necessary pin names coressponding to switches and leds. (e.g. For an and gate : input1: PIN_H5, input2: PIN_J6 and output PIN_J1.
• Now time to compile it.
• Under the Task Window. If everthing is fine, double click "Compile Design". Now just one step: Programming the FPGA board.
• Your board has to be plugged in and drivers have to be installed.
• Under Tools menu open "Programmer", Hardware Setup must be your USB-Blaster and Mode: JTAG
• Just Click "Start".

Note that from File->Create/Update, you can create hierarchical design.

Verilog Design...

Verilog Module:

module ALU (output [3:2] Result, output Cout, output equal, input [3:0] In1, ...); 

 this looks like a struct or class definition correspondingly in C, C++ or Java languages. In order to connect to componets, use "wire".

1)Structural Style

module mux_4_to_1 (Out, In0, In1, In2, In3, Sel1, Sel0)

output Out;

input In0, In1, In2, In3, Sel1, Sel0;

wire NotSel0, NotSel1;

wire Y0, Y1, Y2, Y3

not (NotSel0, Sel0);

not (NotSel1, Sel1);

and( Y0, In0, NotSel1, NotSel0);

.

.

endmodule

2)Data Flow Style ->Using assign

3)Behaviral Style ( better and easy to write ) ->Using always

Verilog - Numbers -> <size> <radix> <value>

3'b001 -> 3 bit binary number; 8'hAB -> 8bit Hexadecimal 0xAB; 124

Binary->b or B; Octal->o or O; Decimal-> d or D; Hexadecimal ->h or H

Verilog has 4 valued logic system -> (0, 1, z, x) z: High impedance, x: Don't care

Two kinds of variables: wire and reg.

Bus example: 

reg[31:0] a; //32 bit wide reg type bus

wire [7:0] b; //8 bit wide wire type buse

wire temp; //1 bit net type signal

Operator example:

reg [7:0] temp = b01001100;

b=&temp; //temp[0]&temp[1]&temp[2]......

Blocked and Non-Blocked Assignments

Non-Blocked:

always @ (*)

    begin

          b<=0; c<=0;

          b<=a+a;

     end

Blocked:

always @ (*)

    begin

          b=0; c=0;

          b=a+a;

     end

Note that in an always block, you have to choose blocked or non-blocked, just one of them.

Note that in every branches of if/else blocks, you have to re-assign all values which you assigned before. If you don't, you cause latches. FPGA does not have latches.

Verilog-Synchronous Logic: (posedge, nededge)

D-FlipFlop Example:

module DFF(input d,clk,output reg q);

always @ (posedge clk)

begin

     q<=d;

end

endmodule

Verilog Example (Altera DEO Board)

module DE0_TOP

(

//////////////////////// Clock Input ////////////////////////

input CLOCK_50, // 50 MHz

input CLOCK_50_2, // 50 MHz

//////////////////////// Push Button ////////////////////////

input [2:0] BUTTON, // Pushbutton[2:0]

//////////////////////// DPDT Switch ////////////////////////

input [9:0] SW, // Toggle Switch[9:0]

//////////////////////// 7-SEG Dispaly ////////////////////////

output [6:0] HEX0_D, // Seven Segment Digit 0

output HEX0_DP, // Seven Segment Digit DP 0

output [6:0] HEX1_D, // Seven Segment Digit 1

output HEX1_DP, // Seven Segment Digit DP 1

output [6:0] HEX2_D, // Seven Segment Digit 2

output HEX2_DP, // Seven Segment Digit DP 2

output [6:0] HEX3_D, // Seven Segment Digit 3

output HEX3_DP, // Seven Segment Digit DP 3

//////////////////////////// LED ////////////////////////////

output [9:0] LEDG // LED Green[9:0]

);

//=======================================================

//  REG/WIRE declarations

//=======================================================

//=======================================================

//  Structural coding

//=======================================================

//assign LEDG[3:0] = SW[3:0] & SW[7:4];// This ANDs switches...

//port by order

and_structural and1(SW[0],SW[4],LEDG[0]);

and_structural and2(SW[1],SW[5],LEDG[1]);

and_structural and3(SW[2],SW[6],LEDG[2]);

//port by name

and_structural and4(.q(LEDG[3]),.a(SW[3]),.b(SW[7]));

endmodule

//STRUCTURAL

module and_structural(input a,b, output q);

   and u1(q,a,b);

endmodule

In task bar, click NetListViewer- RTL viewer to see as a schematic:

End of first day!..